DESIGN OF LOW POWER VEDIC MULTIPLIER BASED RECONFIGURABLEFIR FILTER

  • Janani.M et al.

Abstract

Filter section it plays a major role in Digital Signal Processing(DSP) and image processing
applications etc…high order FIR filters is performed for fixed and reconfigurable
applications.A transposed form block FIR filter contains adder, inner product unit (multiplier),
Coefficient Storage Unit (CSU) and register units. The coefficients are stored in the CSU of the
significant number of channels to be used for the reconfigurable application.The reconfigurable
FIR filter is designed with an array multiplier. So it provides high (area) and high power
utilization. To overcome this problem, the reduced Vedic multiplier is composed by urdhva
tiryagbhyam technique. Vertical and horizontal multiplication is carried out to reduce the partial
product generation stages. Finally, this reduced Vedic multiplier Funit is applied into the
transposed form block FIR filter to achieve the low area, delay and low power.

Published
2020-03-06