Implementation of 16 bit ALU with three different multiplier algorithms and power optimization technique using Xilinx Power Estimator

Abstract

ALU is a key component in any data processing units like real time embedded systems, digital signal
processing units, etc,. The complex and time consuming part of an ALU is the multiplier unit. The main
restrictions of such a multiplier is offering -- high speed, low power consumption and fewer silicon area
occupation or perhaps a mixture of all these in one multiplier and making it suitable for various high
speeds, low power applications. A simple way of multiplication uses both “addition and shift” operations.
The key performance of any multiplier is the number of summation circuit required for the addition of
partial product, which is the most significant term. Number of partial product terms can be reduced by
using Radix-4 algorithm, whereas by using Wallace Tree multiplication methodology one can achieve
with deduction in the usage of more number of successive adders for the intermediate product result
summation and which improves the speed of operation. Reduced speed, increased silicon area for the
implementation will happen sometimes as a result of increase in parallelism , and the quantity of
shifts between the intermediate products will also get increase, which finally ends with more power
requirement for its operation resulting from complex routing . In this paper three different the
multiplication algorithms in a 16-bit ALU are implemented using VHDL code and their parameters like
speed, area, power or the combination of these metrics were measured.