TY - JOUR
AU - Nalini.D , Pradeep Kumar.P , Ramesh.M ,Sundar Ganesh C.S,
PY - 2020/04/13
Y2 - 2024/08/08
TI - Implementation of 16 bit ALU with three different multiplier algorithms and power optimization technique using Xilinx Power Estimator
JF - International Journal of Advanced Science and Technology
JA - IJAST
VL - 29
IS - 6s
SE - Articles
DO -
UR - http://sersc.org/journals/index.php/IJAST/article/view/11042
SP - 2262-2268
AB - ALU is a key component in any data processing units like real time embedded systems, digital signalprocessing units, etc,. The complex and time consuming part of an ALU is the multiplier unit. The mainrestrictions of such a multiplier is offering -- high speed, low power consumption and fewer silicon areaoccupation or perhaps a mixture of all these in one multiplier and making it suitable for various highspeeds, low power applications. A simple way of multiplication uses both “addition and shift” operations.The key performance of any multiplier is the number of summation circuit required for the addition ofpartial product, which is the most significant term. Number of partial product terms can be reduced byusing Radix-4 algorithm, whereas by using Wallace Tree multiplication methodology one can achievewith deduction in the usage of more number of successive adders for the intermediate product resultsummation and which improves the speed of operation. Reduced speed, increased silicon area for theimplementation will happen sometimes as a result of increase in parallelism , and the quantity ofshifts between the intermediate products will also get increase, which finally ends with more powerrequirement for its operation resulting from complex routing . In this paper three different themultiplication algorithms in a 16-bit ALU are implemented using VHDL code and their parameters likespeed, area, power or the combination of these metrics were measured.
ER -