Performance Analysis of D-flipflop and 4*1 Mux Employing Improved SVL Technique
The expectation for low power memory circuits can be achieved by reducing leakage current which is the main cause for power dissipation. Basically when the circuit is switched from active to stand-by mode, substrate voltage of the PMOS transistor raises from VDD to 2VDD likewise NMOS transistor raises from GND to VDD to improve this voltage supplied in stand-by mode must be reduced. By incorporating Improved self-controllable voltage level technique along with body biasing reduces leakage current in stand-by circuit and active circuit. SVL circuit is less intricate to implement Uses less number of transistors and supplies maximum dc voltage in active mode and decreases the dc voltage in stand-by mode. This paper proposes the design of Data flip-flop and 4*1 multiplexer fitted with SVL and ISVL circuit in cadence virtuoso tool in 45nm technology which reduces the leakage current and power consumption and further increases the circuit reliability.