Dynamic Power Estimation for FPGA Based Traffic Signs Detection Models

  • Prachi Dewan, Neeraj Shukla, Rekha Vig


Field programmable gate array (FPGA) devices peculiar property of parallel computation can be effectively exploited in its real-time image- based applications. In this domain, real-time traffic sign detection models embedded on a chip can be of high concern as it will assist the drivers while driving. Due to more and more complexity on a single small chip, both power and performance assessment has become a major challenge The article    encapsulates a systematic method of finding the total dynamic power consumption of various Simulink models already implemented on Spartan 3E Digital signal processing (DSP) XC3S500E development board at 100MHZ clock on 90nm device technology, for detection of traffic signs using the XPower Analyzer  as a computer- aided design (CAD) tool.  It can be concluded that the on-chip power can be reduced by reducing the design frequency of the FPGA.

Keywords: Xilinx Power Estimator Tool, Matlab, Hardware Description Language, Xilinx System Generator, Digital Signal Processing, Image processing, Dynamic power

How to Cite
Rekha Vig, P. D. N. S. (2020). Dynamic Power Estimation for FPGA Based Traffic Signs Detection Models. International Journal of Control and Automation, 12(5), 402 - 409. Retrieved from http://sersc.org/journals/index.php/IJCA/article/view/2644