Comparison of Power and Latency Optimised 7T SRAM with Fully Differential 10T SRAM bit-cell
Static Random Access Memory (SRAM) is an essential and vital component of any modern digital system. Modern digital systems require portability. Portability is possible only if the system can be battery operated and the battery life is long enough. To ensure long battery life of a system the power consumed by the system should be as minimal as possible. Major portion of the power consumed by a digital system is due to the SRAM of the system. Hence majority of the research is directed toward the reduction of power consumed by SRAM. Here in this work an effort is made to reduce the power consumption of a 7T SRAM. An effort is made to attain this goal without compromising on the performance aspect of the SRAM. Here a 7T is chosen because of the reasonably high density and acceptable stability that it offers. To have reasonable density and stability a 7T is chosen as the architecture of choice for implementation. Here a novel 7T SRAM cell has been designed having both low latency and low power. The proposed SRAM bit-cell architecture has allowed control over Threshold voltage, and also reduced the leakage current. As a result, there is a reduction in the static power consumption and load capacitance of SRAM. The 7T is compared with 10T SRAM bit cell. On comparison of the performance parameters, the proposed 7T SRAM cell was found to be the cell with the least power consumption along with the lowest latency among the two cells. This research was carried out using Cadence Virtuoso Tools on 90nm technology with Assura Verification tool and Spectre simulation tool.