Multiplier Based on BST for High-Performance Compression

Abstract

Approximate computing can increase the performance and power efficiency with decrease with the quality of the look for the error free applications. Binary stacking tree be used to reduce the errors. This proposal deals with a latest vogue approach for approximation multipliers. The binary stacking tree uses 3-bit stacking circuits, that cluster all the ‘1’ bits on. The bit stacks square measure then regenerates to binary counts, producing 6:3 or 7:3 counter circuits with no XOR gates. This proposed system will reduce the power savings of more than 78% and area savings of 32% compared to an existing system. Mean relative errors are expected to be lower than 7.6%.