FPGA Based Multi-Level Image Thresholding using Neural Network Optimization Algorithm

Abstract

This paper represents an effort to create segmentation of images using FPGA.The EDK code based
on Xilinx platform is built on the FPGA Vertex 7 and images segmentation is considered one of the
most essential processes in the production of images.Matlab based software is used to transform the
image into the bit stream array that will be used as the Xilinx device studio header format. In the
present situation image processing is one of the huge developing fields. It is a strategy which is
ordinarily used to improve raw image which are collected from different assets. It is a sort of sign
processing. Many of these strategies use only the histogram of the gray scale, while others use
analytical solutions of the Fuzzy set. In noisy environments these methods are not appropriate. This
paper gives an outline of image processing techniques.The experimental results showed that the
FPGA has taken less time to segment the image segmentation than MATLAB. MATLAB, Simulink and
XSG merge in this architecture. XSG is used to implement the hardware design, while the software
component is built using Matlab.