Design and Implementation of Low Power 8x8 Array Multiplier with Proposed CORDIC Algorithm architecture
Abstract
In today’s VLSI system design apart from performance and area, power consumption has also become a major deal for any designer. Circuits with low power consumption for design of microprocessors and system-components have become the major challenge. Multiplication is the basic fundamental operation in most of the arithmetic computing systems. Multipliers always have large occupied area, with long latency and consume abundant power in the circuit. In this paper, a special technique is carried out to reduce the number of multipliers by using Volder designed algorithm which is named as CORDIC algorithm from this we can achieve less multiplier architecture. An 8x8 array type multiplier is designed by using CORDIC The Proposed architecture shows large reduction in terms of power, area, and delay and later these multipliers are compared with different other algorithms to demonstrate the work. The simulation results are carried out by ISE Xilinx.