Desıgn And Performance Analysıs Of Ternary Half Adder Based On Ternary Multıplexer Prımıtıves And Ternary Logıc Prımıtıves

Abstract

Integrated circuits are in demand to be invetigated for its economical performance. Therefore, it is vialbe to experiment on ternary based operations[7]. A ternary half adder based on ternary multiplexer and logic primitives is proposed and its performance is analyzed in detail. This proposed ternary half is sensibly designed with the simplified expressions using the ternary k-map. The combinational logic blocks for the SUM and CARRY are designed, verified, constructed and simulated with Tanner EDA (130nm) at 1.2 V.