Array Multiplier Using Multiplexer based Pass Transistor Logic Style Full Adders

  • Mr. K. Sudhakar, Mr. S. Arunprathap


            For designing the high speed and low power multiplier are normal in layout of extensive research significance. An arithmetic logic unit is the combinational logic electronic circuit that performs the arithmetic and logical operation by using binary numbers, ALU is the heart of the CPU, It performs the addition, multiplication and all compression operations. The all ALU operations multiplication is a complex operation which can be done by full adders. In digital circuits the multiplication process consumes the large power compare to other operations. In multiplier concept, there are many ways to moderate the partial products in multiplication procedure among that one of the important method is array multiplier. The hybrid logic style full adder design is based on the new 14 transistor structure. The proposed full adder circuit design is based on the multiplexer, which reduce the number of transistors in the design, less capacitance effect and high driving capacity. In array multiplier major role is full adder functions, which determines the multiplier function In this paper new multiplexer based logic style full adder functions are analyzed and used in the array multiplier.