FPGA BASED DIGITAL LOGIC ANALYZER FOR DIGITAL AUTOMATIC TEST EQUIPMENT
Simulation is necessary to identify the defects in most of the digital circuits before the final unit is formed. The process of simulation generally caters for displaying logic analysis. Usually, discrete logic circuits which are complex in nature are verified by input simulation and testing of outputs by boundary scan methods. Logic analysers used for such purposes may uncover hardware defects that are not found in simulation. This work covers design and simulation of Digital logic analyser and its sub modules Dual Port Random Access Memory (DPRAM), Parallel to serial converter (PTSC), Multi Standard Baud Rate Generator and Universal Asynchronous Receiver Transmitter (UART). Simulation is done using Xilinx ISE 14.5v EDA tool and FPGA implementation is carried out on Xilinx Spartan3 FPGA board.