FPGA Implementation of Proficient Lightweight Architecture for Present Block Cipher
Cryptography is a mathematical based technology and extremely rich to ensure that several concepts of the information security over a public channel. They have been deployed in diverse areas for every conceivable purpose. Present days the cryptography plays an essential role for secured data transmission. The proposed design has high performance Lightweight VLSI architecture for block cipher with 2x80-bit key. This architecture increases the throughput by reducing the latency up to 50% from the existing architectures, so that it can improve the performance of the designed architecture. Here it has been observed that the number of clock cycles of latency is 32 cycles. The FPGA with onboard clock frequency of 250 MHz achieved the throughput of 1Gbps. The entire architecture is designed using Verilog HDL. The simulation, synthesis and implementation on FPGA is done with Xilinx ISE design suite.