Functional Verification of Enhanced Video Compression by Using H.265/HEVC Standard Using 45nm Technology
This presented paper implementation was optimized architecture of the inverse quantization and the inverse transform for a High-efficiency video coding (H.265/HEVC) decoder. In this design to develop the parallel and pipelined architecture was designed to support transform unit 4 × 4, 8 × 8, 16 × 16 and 32 × 32. The quantization and inverse transform described in RTL design using Verilog using Cadence tool with 45nm technology. The simulation results carried out for ram module in dequantizer which is used for to store the high compression rate of any data. The throughput of the current architecture reached in the worst case a processing rate of up to 1090 p at 35 fps at 200 MHz and 1080 p at 40 fps at 220 MHz when mapped to standard cells respectively. The validation of our architecture was conducted using a Software Cadence environment in order to evaluate different implementation methods in terms of power consumption and run-time. The experimental results demonstrate that the above designs were enhanced by more than 80% in terms of the run-time speed relative to the existing solution. Besides that, the power consumption of the current designs was reduced by nearly 70% compared with the other methods.