FPGA implementation of low power 16x16 bit Vedic Multiplier

  • S. Ravi , P. Murugapandian , T. Lavanya Devi , D. Venkata Anil ,B. Ravi Teja , P. Maneesha


This paper proposes a vedic multiplier based on Urdhwa Tiryagbhyam sutra. This sutra can be used to perform multiplication on large size input in a very fast manner. The implementation follows hierarchical approach, that is the design process starts with 2x2 multiplier design, then it is used in the implementation of 4x4 multiplier. The same thing continues for 8x8 and 16x16 multipliers design. As a part of the implementation in FPGA process, synthesis report of the proposed system is obtained and the hardware utilization details are presented.