Hardware Implementation of Image Denoising Using AIQR Technique
Image denoising is one of the fundamental steps in the processing of images. The defects in the image acquisition process result in adding the salt and pepper noise to the image at some fixed points leading to the degradation of image quality. Adaptive Median filter is one of the most widely used filters, in the
literature, for the removal of salt and pepper noise which was implemented in FPGA. The Inter Quartile Range filter is a nonlinear spatial filter aims at removing the noise by preserving the edge information. In this paper, modified Adaptive Inter Quartile Range (AIQR) filter is presented for the removal of salt and
pepper noise. Real time image processing requires huge amount of operations and high throughput rate. Due to the limitations in the hardware, the algorithm is modified making it feasible for the FPGA implementation while retaining the original features of the AIQR. The hardware implementation of the
proposed algorithm aims at achieving high speed with minimum area. To prove the robustness of the proposed filter, it is done state of art comparison with the existing spatial domain denoising techniques. The results demonstrate superiority of the proposed filter over other competing filter topologies with respect to resource utilization, PSNR and SSIM.