A Novel FPGA Implementation Of Error Reduction In 8,16 And 32-Bit Scalable Approximate Rounding Based TOSAM (3,7) And (4,8) Multiplier

  • G. Erna, S. Tamilselvan


In recent technology of Arithmetic application will have number of approximate multipliers,
approximate adders, this work will reduced the complexity in those approximate multiplier and adder
by way of uniqueness approach to compact area, delay and power. In the Scalable method of
approximate signed and unsigned multiplier in truncated rounding technique will present to reduced
number of logic gates in partial products with help of leading one bit architecture. In the approximate
signed and unsigned multiplication design be perform with using arithmetic operation, truncation
operation, absolute operation for shift with add accumulation. In this process of TOSAM will have
number of modes it will differentiate based upon height (h) and truncated (t) such as (h,t) it will
described in the architecture TOSAM(0,2), TOSAM(0,3), TOSAM(1,5), TOSAM(2,6), TOSAM(3,7),
TOSAM(4,8), TOSAM(5,9). Here this TOSAM Operation include more absolute error in the LSB data
shift Unit, thus proposed line of attack will customized in all the arithmetic operations of shift and add
unit with using XOR-MUX Full adder to find a improved solution and reduced the absolute error and it
will proved higher improvements of area and energy utilizations. In this proposed novelty work will
modified approximate signed multiplier architecture as per absolute error reduction in TOSAM (3,7),
TOSAM (4,8), TOSAM (5,9) and consequently prove the compared terms of area, delay and power. To
conclude this work will designed in Verilog HDL and simulated in Modelsim, Synthesized in Xilinx