Processing Discrete Cosine Transform using Coordinate Rotation Digital Computer CoProcessor on Field Programmable Gate Array
With the rapid growth of digital signal processing (DSP) applications, there is a high demand for efficient implementation of complex arithmetic operations. In last five decades, a Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely adopted to formulate and implement a variety of DSP algorithms for reconfigurable computing. In this paper, a CORDIC coprocessor was implemented on Field Programmable Gate Array (FPGA), to accelerate the performance of several arithmetic computations such as multiplication and division, as well as 11 elementary transcendental functions. As CORDIC algorithm suffers from limitations for its convergence domain and speed, the unified argument reduction algorithm and the hybrid angle method were adopted. The coprocessor was integrated into NIOS II soft processor to develop a NIOS II-based embedded System-on-Chip (SoC), designed on Altera DE0 board running at 50MHz of clock frequency. The experimental results showed the performance improvement of approximately 553 times was achieved while executing one dimensional Discrete Cosine Transform (DCT) algorithm using the developed coprocessor.