VLSI Design of Area Efficient Test Data Compression Architecture for IoT Devices

  • S. Anandhi2, R. Neela, M. Janaki Rani


Internet-of-Things combines the functions from sensing the environment and computing the sensed data followed by storing it and finally communicating the computed data periodically or in a critic situation. The network architecture of IoT is a complex architecture as an IoT system combines the nodes from cloud computing and fog to create its communicating network. VLSI increases the functional ability of trending technologies like Iot and SoC for their numerous applications. VLSI devices are the key for the success of many emerging green technologies.  As size of the system plays a critical role in both economical and functional success of a system, VLSI helps in these promising areas for its implementation. Many researchers have proposed numerous compression techniques. Code based compression scheme is one among them. Run length coding is one of the most promising techniques in code based compression scheme. In the proposed methodology, a hybrid compression technique is proposed. First Golomb coding is used to compress the data. The compressed data is further compressed using dictionary based compression code. The obtained compression ratio through hybrid data compression using Golomb and Dictionary based compression code is further compared with other compression techniques. The simulation results show that hybrid compression technique achieves an increased compression ratio of 75.89%.

How to Cite
M. Janaki Rani, S. A. R. N. (2020). VLSI Design of Area Efficient Test Data Compression Architecture for IoT Devices. International Journal of Advanced Science and Technology, 29(4s), 628 - 639. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/6409