Design and Implementation of Low Power 16x16 Multiplier using Dadda Algorithm and Optimized Full Adder

Abstract

 Low power circuit designs have been an important issue VLSI design areas. Multipliers play a major role in high performance systems. The Dadda tree multiplier is considered as faster than a simple array multiplier and is an efficient implementation of a digital circuit which is multiplies two integers such multiplier which is effective both in terms of speed and power. Adiabatic logic style is said to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. In this work ECRL (Efficient Charge Recovery Logic) based Dadda tree multiplier is compared with Wallace tree multiplier. Xilinx 13.2i tools are used for simulation and to implement Spartan 3E family