Design and Implementation of Novel Hybrid Adder for Low Cost and High Speed Applications

Abstract

The main intent of this paper is to design and implementation of novel adder for high speed and low cost. Basically, the implementation of novel adder is based in VLSI chips because they are used as critical element.  In the circuits of ALUs, Floating point arithmetic units, memory addressing and program counting, adder’s plays major role. The Novel adders will reduce the trade off occurred between the circuits. Based on the nodes of operation the size of the parallel circuit is determined. The Novel adder is simulated by using VLSI synthesis tool. Hence the proposed Novel adder gives effective results compared to others like RCA.