Low power FPGA implementation of 32- Point RFFT for High-Speed Application

  • Kavitha MV, S.Ranjitha, Dr Suresh H N


          In today’s innovative technology, area, power and delay are the major parameters to design any kind of the algorithm on Field Programmable Gate Array (FPGA). In communication and Biomedical fields, Fast Fourier Transform (FFT) has the major role in obtaining the signal characteristics with minimum use of resources. Some of the algorithms have been proposed onFFT, such kind of algorithms were less effective in the performance parameters. In this paper, Real FFT with Dual Port Random Access Memory using Ladner Fisher Adder (RFFT-DRAM-LFA) method is introduced to perform FFT operation and improve the Application Specified Integrated Chip (ASIC) and Field Programmable Gate Array (FPGA) performance. Radix-8booth multiplier is used to perform the multiplication operation.  This proposed architecture achieved 1085 LUT, 60 flip flop, and 585 slices. All the FPGA performances are improved in RFFT-DRAM-LFA method compared to conventional methods.

How to Cite
Dr Suresh H N, K. M. S. (2020). Low power FPGA implementation of 32- Point RFFT for High-Speed Application. International Journal of Advanced Science and Technology, 01 - 18. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/3302