Design and Implementation of High-Speed Vedic Multiplier Using Hybrid Full Adder

Abstract

Multipliers plays an important role in today’s digital signal processing and various other applications. Designing of Multipliers which offer high speed, low power consumption and less area is essential in today's VLSI systems. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this work, Vedic multiplier is designed using Urdhva Tiryagbhyam Sutra which is most efficient to give minimum delay. Here, a modified low voltage high performance hybrid full adder is used to reduce delay and area. The comparison of hybrid adder with compressors is also carried out in terms of performance. Delay, area, power and PDP of hybrid adder have been reduced by 11.12%, 7.04%, 1.46% and 12.67% respectively when compared with conventional full adder. This design has been simulated and verified using DE2-115 FPGA kit.