Design and Implementationof Low Power VLSI FinFET Dynamic Latch Comparator for ADC Application

  • Praveen J, Raziya Banu, Rashmi KB, Varshini MN, Soundarya NA

Abstract

One of the most significant circuits among analog integrated circuits is the comparator. The significant issue during designing of the comparator is power dissipation. Analyzing the performance of the existing conventional comparators, for the application of Analog to Digital Converters (ADC) like flash ADC. The power issues can overcome by using the proposed comparators which uses Fin Field Effect Transistor (FinFET) technology. The FinFET technology has the remarkable gate control feature towards the region of the channel. In this paper, at first the four existing conventional dynamic latch comparators are designed for which the power is calculated. Then these existing conventional dynamic latch comparators are upgraded into the proposed structured utilizing FinFET innovation for power is calculated, since power is a significant worry in the comparators. These existing conventional comparators and the proposed comparators using FinFET are simulated and designed using the cadence virtuoso version 6.1.5 for GPDK 180nm CMOS technology.The conventional dynamic latch comparator consumes 4.273µw power, but proposed dynamic latch comparator using FinFET technology consumes 1.592 µw, thus in the proposed design 62.74µw reduction of power compared to conventional comparator.

Keywords: FinFET, Latch, Comparator, CMOS, ADC, Cadence Virtuoso.

Published
2020-06-06
How to Cite
Praveen J, Raziya Banu, Rashmi KB, Varshini MN, Soundarya NA. (2020). Design and Implementationof Low Power VLSI FinFET Dynamic Latch Comparator for ADC Application. International Journal of Advanced Science and Technology, 29(08), 5046-5055. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/26839
Section
Articles