A Design and Implementation of Adiabatic Logic on Low Power Application Circuits
The relevant decision of flip-flops topologies is of fundamental significance in the structure of Very Large Scale Integrated (VLSI) and Complementary Metal-Oxide Semiconductor (CMOS) circuits. Breaking down the conduct of existing customary flip-flops and picking the best flip-flops for the predetermined application is a fundamental issue to finish the requirement low power circuit. The D-flipflops is the most important block in synchronous counters with excessive power utilization influence the general effectiveness of the system. This power dissipation can be diminished by utilizing the adiabatic technique. In this paper existing [1-5] flip-flops are designed first, for which delay, power and area are calculated. Then these existing flip-flops are newly proposed by using an adiabatic technique for which again delay, power and area are calculated. The design of these existing and proposed is designed by using Cadence Virtuoso Schematic Editor and Analog Design Environment (ADE) for 180nm technology with a supply voltage of 1.8V and 100MHz frequency. The existing D-flip flop consumes 16.6µW power, but the newly proposed circuit consumes 1.06µW, which results in power reduced by 93.59%, delays reduced by 7.47% and the area remains the same compared to an existing design.
Keywords: Filp flops, VLSI, CMOS, Domino Logic, Cadence.