A Novel Approach For Analysis CNTFET Based Domino circuit in Nano-Scale Design

  • Namrata Sharma, Dr. Uday Panwar

Abstract

As semiconductor industries is developing day by day to meet the requirement of today’s world.  As scaling of ICs day by day to introduce functionality of the device while fabrication more and more component which results in shorter the life of the battery operated device which has to be improved. Here in this article we have measured performance parameters like power consumption, UNG, Evaluation Delay, standby power and speed of various domino circuits provided for various inputs like 8 &16 input OR gate. When we compared power, delay, and PDP of different topologies of domino circuit design with the simulation results which is performed by using SPICE tool at 32nm CNTFET process technology with supply voltage 0.9V and 27⁰ C of temperature at 100 MHz. All the simulation results is done in CMOS & CNTFET technology, it is observed that saving of average power upto 90.46% with same delay, with improvement of 5.8 × Noise-immunity with scaling of technology.

Published
2020-06-01
How to Cite
Namrata Sharma, Dr. Uday Panwar. (2020). A Novel Approach For Analysis CNTFET Based Domino circuit in Nano-Scale Design. International Journal of Advanced Science and Technology, 29(7s), 5898-5908. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/26512