Implementation Of 24-Bit Delay And Area Efficient Enhanced Equal Segment Adders
The proposed work presents the enhancement of the general architecture of an n-bit approximate adder done using the carry predictor unit. The simulation is carried out using the Xilinx ISE 14.7 environment. The aim of the proposed work is to determine the carry block output. The paper also presents the comparative analysis of ESA based 24-bit Ripple carry adder, Kogge stone adder and carry increment adder with emphasis on area, delay and power consumption based on ESA structure with and without overlapping.