An efficient design of Multiplier in Quantum-dot Cellular Automata Technology using Majority Logic
The CMOS transistor-based multipliers are restricted in terms of channel width at certain levels as compared to their present size. These restrictions cause power, speed limitation in the design. By incorporating the new technology i.e., the Quantum-dot Cellular Automata at nano metric scale the size and hence area can be reduced with Low Power Consumption using the concept of Quantum cells. The QCA approach is one of the best arrangements in beating this physical width and channel width. Any digital logic can be performed using QCA based majority gates. In the present work fast adders like parallel prefix adders using compressor methodology and multiplication operations are performed by utilizing Majority gates. The designed multiplier is effective and efficient in terms of area-delay tradeoff, delay(speed) and power utilization.