High Performance Design of Wallace Tree Multiplier using Hybrid Adders
Multiplication is one of the complex arithmetic operation in digital circuits. In order to design a high-performance system, multipliers used in those circuits are to be designed efficiently. Among several multiplier topologies, the Wallace Tree Multiplier performs the efficient implementation of multiplication. In such a multiplier, the adder is the main block whose speed affects the performance of entire circuit. In this paper, the basic full adder block in Wallace Tree Multiplier structure is replaced with the proposed hybrid adder to achieve high performance. The proposed Wallace Tree Multiplier is designed for performing multiplication of both 4 – bit and 8 – bit using Verilog HDL. The design is verified and simulated functionally in terms of delay(ns), Logic elements used and power (mW) using Xilinx design suite. And the Wallace Tree Multiplier designed using hybrid adder is proven to produce lesser delay (ns) of about 25% and power (mW) of about 12% compared to all other designs.