Design of SRAM at Deep Submicron TechnologyNode

  • Sunny Saykar, Satish Sonwale, Sachin Yadav, Varsha Bendre

Abstract

SRAM Architecture design using 90nm, 45nm, 130nm CMOS technology has been proposed. From the last few decades, the scaling down of CMOS devices have been taking place to acquire better performance. The scaling of CMOS technology has cogent impacts on SRAM cells. The SRAM uses a bi-stable latching circuitry to store the logic data 1 or 0. It differs from Dynamic RAM (DRAM) which requires periodic refreshing operation for the storage of logic data. The SRAM architecture have 6T Memory cell, precharge circuit, write driver, address decoder, sense amplifier respectively. Testing and simulation is carried out in LTspice tool using CMOS technology

Published
2020-06-04
How to Cite
Sunny Saykar, Satish Sonwale, Sachin Yadav, Varsha Bendre. (2020). Design of SRAM at Deep Submicron TechnologyNode. International Journal of Advanced Science and Technology, 29(9s), 7351-7360. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/24485