Design and implementation of low phase noise, wideband clock source for high speed data converters

  • Sk Anusha, M.Krupa Swaroopa Ranı, K.M.V.Prasad
  • Sk Anusha, M.Krupa Swaroopa Ranı, K.M.V.Prasad3

Abstract

Noise is the main parameter in the Phase locked loop (PLL). The main purpose of this paper is to design and implementation of integrated VCO frequency synthesizer that achieves less noise, wideband and extremely low spurious performance using the HMC830LP6GE Fractional-N- Phased-Locked-Loop (PLL). HMC830 attributes an Integrated voltage controlled oscillator (VCO) with a necessary range of Frequency from 1.5 GHz - 3 GHz, and the divider of Integrated VCO output (divide by 1/2/4/6.../60/62), that a mutually permits the HMC830LP6GE to produce the range of Frequencies from 25MHz - 3GHz. The Integrated phase detector (PD) and Delta-Sigma modulators are having the ability of working up to 100 MHz; allow bandwidths of Wider Loop with good spectral achievement.

Index Terms: PLL, VCO, Integrated phase detector, Serial Peripheral Interface (SPI), delta-sigma modulator, Phase noise, Spurious, HMC830

Published
2020-06-06
How to Cite
Sk Anusha, M.Krupa Swaroopa Ranı, K.M.V.Prasad, & Sk Anusha, M.Krupa Swaroopa Ranı, K.M.V.Prasad3. (2020). Design and implementation of low phase noise, wideband clock source for high speed data converters. International Journal of Advanced Science and Technology, 29(7s), 4338-4350. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/22959