Energy Effıcıent Floatıng Poınt Unıt for Multımedıa Applıcatıons
Floating Point Unit (FPU) is at core of all the modern DSP processors to process floating point information of multimedia applications. This article presents energy efficient architecture to perform 32-bit floating point arithmetic operations. The presented architecture has been designed by considering 32 bit single precision IEEE 754 standard to represent the floating point data and also it describes how arithmetic operations are performed. The proposed FPU takes data, called operands, to be operated on and a code indicates which operation to be performed and computes the results. The proposed architecture has been implemented on FPGA device, results are verified and the parameters like area and speed has been analyzed.
Keywords: Floating Point Unit, Field Programmable Gate Array, and IEEE 754 standard