Physical design implementation of RISC Processor Subsystem

  • G.Lakshmi Samhitha, Dr.T. Vigneswaran, Dr.V.Ravi

Abstract

A reduced instruction set is a set of instructions, which causes the microprocessor of a computer to have lesser cycles per instruction (CPI) than a Complex Instruction Set Computer (CISC). Reduced instruction set computer’s (RISC) most distinguish feature is that the instruction set is designed for a very regular flow of pipeline instruction. Another common feature of RISC is its load/store architecture in which memory is loaded by specific instructions instead of as part of most instructions. The design components regarding the RISC subsystem with their geometric representations are instantiated during physical design flow. Physical design flow is implemented with all the stages namely floorplan, placement, Clock Tree Synthesis (CTS), Routing and signoff is implemented in 14nm technology.

Keywords: Reduced instruction set computer (RISC), floor plan, placement, Clock Tree Synthesis (CTS), Routing, Engineering Change Order (ECO).

Published
2020-06-06
How to Cite
G.Lakshmi Samhitha, Dr.T. Vigneswaran, Dr.V.Ravi. (2020). Physical design implementation of RISC Processor Subsystem. International Journal of Advanced Science and Technology, 29(4s), 2916 -2928. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/22228