Design and Verification of Half Adder using Look Up Table (LUT) in Quantum Dot Cellular Automata (QCA)

  • Chella Santhosh, R. S. Ernest Ravindran, Uday Bhanu

Abstract

Addition is the basic arithmetic operation that is used to perform complex operations. CMOS based chips, uses the transistor voltages to obtain the outputs are very efficient for these operations. In this research a new design of half adder circuit is implemented using look up tables, as LUT’s decrease the processing time and produce better output swings. Half adder circuit using LUT is designed by less cell count that reduce the area of the entire HA thereby reducing the delay and increasing the efficiency of the whole circuit. Half Adder circuit is implemented using QCADesigner Software tool.

 Keywords: half adder, quantum cellular automata, logic gates, multiplexer, look-up table.

Published
2019-12-21
How to Cite
Uday Bhanu, C. S. R. S. E. R. (2019). Design and Verification of Half Adder using Look Up Table (LUT) in Quantum Dot Cellular Automata (QCA). International Journal of Advanced Science and Technology, 28(16), 1804 -. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/2201
Section
Articles