Implementation of Reconfigurable FIR Filter using Logic Optimization Technique
The design and implementation of FIR Filter is attaining prominence in digital communications because of its characteristics like BIBO and Stability. Voluminous improvements procured in the VLSI architectures design for FIR Filter for the purpose of reconfiguration. In the real–time implementation of Reconfigurable FIR filters, the accuracy of the acquired signal is achieved by increasing the order of the filter which leads to increase in area .Though the prevailing RFIR Filter designing techniques are effective in various performance metrics, there is still a chance for such a filter design to achieve area efficiency. In this paper, Reconfigurable FIR filter (RFIR) architecture is designed by employing different MAC’s. Simulation and synthesis are carried out using the Cadence Encounter tool. Comparison of Reconfigurable FIR Filters (RFIR) employing different MAC’S is performed. From Result analysis, it is observed that RFIR Filter employing Vedic multiplier based on yavadunam sutra and SQRT-CSLA-BEC is area efficient RFIR Filter.
Keywords: RFIR Filter, Vedic multiplier, SQRT-CSLA architecture, Area Efficient Architectures