Implementation of Area and Delay Efficient QCA Circuits Using 5MAJ
The modern VLSI design aim at optimization of any of three parameters namely power, area and delay. To achieve this optimization many of the researchers employed CMOS technology. As the technology diverging day by day further optimization of various VLSI parameters is essential to make device smart and power comparative. As a part of optimization of area and power if we try to extend CMOS technology to nanometer range the length and width of the channel becomes too small and hence transistor loses its functionality. As alternative CMOS in nanometer scale a new technology QCA has been developed. QCA is one of the promising technologies that have been employed in modern VLSI design for optimization of power and area. This paper proposes design of multi input multi output 5 majority gate and further the same is employed in design of digital circuits namely Full Adder, RAM memory cell and reversible BCD. This paper aims at reducing area overhead and the obtained results covey fact that there is almost 50% to 60% reduction in area as compared to normal gate level design. Here all the three modules are implemented using free clock scheme and USE clock scheme and conclusions are drawn with respect to area and delay for the designed clock schemes.