Design And Performance Analysis of Modified 1 Bit Sram Architecture

  • B.N. Srinivasarao, Dr. K. Chandrabhushana Rao

Abstract

SRAM cell architectures are complex circuits that consists not only memory cells it consists pre-charge circuit, driver circuit and sense amplifier also. The memory cells are optimized in research to perform its maximum extent in terms of power consumption, area and speed of operation. But the associative circuits are also play a vital role in overall performance especially for full swing of the read and write signals. In this paper an investigation is done on various architectures with 1:1 cell ratio and found reading a 0 and 1 is a big issue in terms of full swing. This paper proposed a design with feasible solution for the same. The proposed design is implemented and analyzed with 45nm technology and achieved the area reduction by 7% and improves the speed about 22% with the average power consumption 1.64µW.

Published
2020-06-02
How to Cite
B.N. Srinivasarao, Dr. K. Chandrabhushana Rao. (2020). Design And Performance Analysis of Modified 1 Bit Sram Architecture. International Journal of Advanced Science and Technology, 29(9s), 6275 - 6284. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/20237