Comparative Analysis of FinFET and CMOS Based 6T Static Random Access Memory Cell
In this paper, FinFET and CMOS based 6T static random-access memory (SRAM) cell has been implemented on 18nm and 45nm technology node with Cadence virtuoso tool. The implemented FinFET and CMOS based 6T SRAM cells offer differential read operation. Different design trade-offs in convention 6T CMOS SRAM cell and 6T FinFET based SRAM cell are also discussed. It has been observed that FinFET based design is more advantageous in terms of reduction in read power, write power and improvement in read signal to noise ratio (RSNM). In other words, optimum performance parameters are obtained with FinFET Technology. The read/write delay, read/write SNM and power delay product of FinFET based 6T SRAM cell are better as compared to conventional CMOS based 6T SRAM cell.