Implementation of Low-Power Built in Test Compression Capabilities in Programmable PRPG

  • D. Manaswi, G. Srilakshmi, K. Kiran,

Abstract

This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to pattern- count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.

Published
2019-12-05
How to Cite
K. Kiran, D. M. G. S. (2019). Implementation of Low-Power Built in Test Compression Capabilities in Programmable PRPG. International Journal of Advanced Science and Technology, 28(16), 641 - 650. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/1895
Section
Articles