A New Cascaded Single Phase Multilevel Inverter Topology with Reduced Switches

  • V. Kubendran, Y. Mohamed Shuai, J. Preetha Roselyn, K. Vijayakumar

Abstract

The new single phase multilevel inverter is designed and analyzed for both symmetric and asymmetric
modes of operation to gets the stepped voltage. Maximized stepped voltage can be obtained by
cascaded connection of all basic units in proposed topology. This topology requires fewer power
electronics switches to attain a specific number of stepped levels. This has been proved and compared
with other conventional topologies. With this topology, the symmetrical 13 stepped levels,
asymmetrical 25 stepped levels have been adequately validated by MATLAB / SIMULINK. The FPGA
based hardware implementation of the proposed inverter topology has been validated along with
simulation results.

Published
2020-05-20
How to Cite
V. Kubendran, Y. Mohamed Shuai, J. Preetha Roselyn, K. Vijayakumar. (2020). A New Cascaded Single Phase Multilevel Inverter Topology with Reduced Switches. International Journal of Advanced Science and Technology, 29(9s), 6011-6019. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/18801