Single Bit 7T Sub-threshold SRAM cell for Ultra Low Power applications
Extensive use of portable low power consuming devices motivates to VLSI designers to develop system on chip design for modern applications. In this paper, PP 7T SRAM cell has been proposed which operates at ultra low supply voltage i.e. in sub threshold, near threshold and super-threshold region. Detailed analysis of SRAM parameters such as stability, delay and power dissipation has been performed with Cadence virtuoso tool at 45nm technology node. It has been observed that read static noise margin (RSNM) of proposed PP 7T SRAM cell is 2.05× and 4.1× improved as compare to conventional 6T and reported 7T SRAM cell, respectively. Read power of proposed PP 7T SRAM cell has reduced by 0.91×/0.66× and write access time improved by 3.22×/1.07× in comparison of Conv. 6T and reported 7T SRAM cell, respectively at 0.5V supply.
Keywords: RSNM, WSNM, Access time, Sub threshold region.