A FPGA Based Acceleration of Bit Parallel String Matching Algorithms
Field Progammable Gate Array based solution has great importance in the a range of string matching algorithms. BNDM and BNDMq are the very easy and single pattern bit parallel string matching algorithms.They play a vital role in many real world problems since they have very significant property of intrinsic parallellism. There are many applications of string matching algorithms, caused by their efficiency improvement BNDM and BNDMq hardware based solution are proposed.They have been proposed on account of being faster than the character based algorithms. This paper, discusses the performance analysis of software based BNDM algorithms and compares them with FPGA based BNDM .The main focus of this paper is to minimize the searching time and achieve high speed by implementing these bit parallel algorithms in hardware using FPGA. Improved FPGA BNDM hardware based string matching algorithm are presented with variations of the BNDM algorithm for approximate string matching. The experimental result conclude that the new variations are faster than previous algorithms in terms of efficiency and speed.