Split Radix Fast Fourier Transform Design with Reduced Multipliers
A new approach of Fast Fourier Transform with reduced multipliers using is proposed in this paper. Split radix FFT of radix- 2/24 with efficient reduction of twiddle factor multipliers is the major modification of our design. In the proposed design least significant multiplications, that is multiplication with w81 replaced by two-point butterfly followed by shift register. This method reduces the overall multipliers for higher order FFT, each of the Complex multiplication is designed by five real additions and three real multipliers. This process reduces the further real multipliers. The proposed data flow designs reduce overall multipliers than the other recent existing designs. The power consumption of the proposed design is low compared to previously existing designs.