Computational Intelligence Techniques For Power Optimization In VLSI Testing

  • Vamshi Krishna Kambhampati, Shaik Saidulu

Abstract

Very-Large-Scale integration is an upcoming field in electronics. It is a process of designing and creating integrated circuits by combining hundreds to thousands of transistors into a single chip. VLSI is not new to the world, it started in last years of 1970. The test intensity of VLSI modules is improved with reordering of the test designs, which have been created through turbo analyzer. A test system for reordering of test examples has been grown in order to diminish the exchanging movement during testing. The methodology has been tried on some combinational and successive benchmark circuits. Power dissipation of VLSI chips is traditionally a neglected subject. For structuring and unraveling complex and very enormous obliged combinational issues in a VLSI Computer Aided Design (CAD) device with ideal arrangements, it is attractive to utilize the capability of EAs to land at ideal arrangements. GA is an incredible strategy to create productive CAD devices for improving the exhibition of format age and IC testing undertakings in VLSI structure. Utilized turbo analyzer for our investigations for the age of ideal arrangement of test vectors which are additionally reordered with a goal to lessen the test control. The methodology exhibited was connected to different combinational and successive benchmark circuits. The flaw inclusion, time and test example used to accomplish the most extreme deficiency inclusion is determined utilizing BIST analyzer and turbo analyzer. The outcomes got for ISCAS85 combinational and successive ISCAS89 benchmark circuits are recorded individually. The relating graphical portrayal of information for deficiency inclusion, number of test vectors and testing time for different benchmark circuits are accessible. The test power has been demonstrated to be streamlined for some combinational and consecutive benchmark circuits by applying GA related to the technique for decreasing Hamming separation. The underlying test vectors produced by Turbo analyzer are reordered with a target to streamline the exchanging movement pace of the CUT. Reenactments results demonstrate that test power is decreased by a normal of 31% and 36% for combinational and consecutive benchmark circuits individually with no effect on deficiency inclusion.

Published
2020-05-07
How to Cite
Vamshi Krishna Kambhampati, Shaik Saidulu. (2020). Computational Intelligence Techniques For Power Optimization In VLSI Testing. International Journal of Advanced Science and Technology, 29(06), 3497 - 3509. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/14150