Design and Implementation of Parallel Array Multipler Using High Speed Adders
Multiplier is the basic fundamental of many high performance systems such as FIR filters and digital signal processors (DSP). From the past so many years, a Digital signal processor (DSP) with computational complexities has been increased for this requirement parallel array multiplier which meets the high performance demands and speed of the system. This work discusses about the Braun multiplier, one type of Array Multiplier using Parallel Prefix Adder (PPA). The Braun Multiplier consists of 9 AND gates, 8 FULL ADDERS (FA) and PPA in its final stage. All the above design are simulated by using Tanner EDA Tools software using CMOS Technology.
Keywords: Braun Multiplier, PPA, FA, CMOS, TANNER EDA.