FPGA Implementation of XOR-MUX Full Adder and Subtractor based Truncated DCT for Audio Processing Applications

  • Radhakrishnan.P, Themozhi.G, Sree Rathna Lakshmi.N.V.S

Abstract

The recent applications in digital technology are to grow rapidly especially image processing and signal processing applications, as it is mandatory to develop with compactable high quality, high speed, less delay and low power consumptions of all complex methods of applications and algorithms.   Image and audio processing are typical application in digital signal processing, due to which this signal compression is commonly used in DCT/IDCT methods. Thus, the method of compression will take more critical logic sizes and power consumptions in VLSI implementation due to the involvement of more number of arithmetic blocks like multiplier, adders and subtractors. The proposed work present a new approach in this DCT based compression technique using truncated multiplications with level synchronous conventional XOR-MUX adders and XOR-MUX Subtractors. Therefore, this proposed work will reduce 50% of logic size and finally this work is developed in VHDL and synthesized in Xilinx FPGA XC6SLX9-2TQG144 with proven  parameters in terms of area, delay and power.

 Keywords: DCT (Discrete Cosine Transform), VHDL( Very High Speed Integrated Circuit - Hardware Description Language).

Published
2020-05-05
How to Cite
Radhakrishnan.P, Themozhi.G, Sree Rathna Lakshmi.N.V.S. (2020). FPGA Implementation of XOR-MUX Full Adder and Subtractor based Truncated DCT for Audio Processing Applications. International Journal of Advanced Science and Technology, 29(06), 2352 - 2367. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/13535