Parametric Optimization of Architectural Modified FIR Filter

  • T.Shanmugaraja, B.Jai Shankar, K.Siddharthraju, K.Murugan, T.Venkatesh, R.Dhivyadevi, M.Supriya

Abstract

In digital signal processing, FIR filters are used with a finite time impulse response and because of it, in a finite time, it settles to zero. Before settling into zero, N+1 precise samples are taken by Nth order discrete time FIR filter’s impulse response. It may be digital, continuous, analog or discrete   FIR filter used in VLSI projects requires low power, low area or low delay for different applications. In order to implement the FIR filter with low area and less delay application in single structure, the proposed architecture which Systolic Architecture along with Associativity is designed in this project. Once the functionality of the FIR filter is verified using Verilog coding, the different architectures are implemented in Spartan in XILINX ISE to obtain the performance analysis. The proposed structure which includes FIR structure designed with Systolic architecture along with Associativity is designed and performance analysis is determined. For 8-tap FIR filter LUT consumed by the Associativity architecture is 77% less than the direct form structure and the delay obtained by the systolic architecture is 60.46% less than the direct form structure for 8-tap FIR filter and LUT consumed by the proposed architecture(Systolic with Associativity )is 28% less than the direct form structure ,the delay obtained by the proposed architecture(Systolic with Associativity ) is 61.38% less than the direct form structure for 8-tap FIR filter. For 13-tap FIR filter the LUT consumed by the Associativity architecture is 19.23% less than the direct form structure and the delay obtained by systolic architecture is 26.46% less than direct form structure for 13-tap FIR filter and LUT consumed by the proposed architecture is 16.92% less than the direct form structure and the delay obtained by the proposed architecture is 26.5% less than the direct form structure for 13-tap FIR filter. So for the architecture with less area and less delay VLSI application the FIR filter designed using Systolic with Associativity can be designed. In future work this architecture can be implemented in Adaptive filter structures.

Published
2020-04-20
How to Cite
T.Shanmugaraja, B.Jai Shankar, K.Siddharthraju, K.Murugan, T.Venkatesh, R.Dhivyadevi, M.Supriya. (2020). Parametric Optimization of Architectural Modified FIR Filter. International Journal of Advanced Science and Technology, 29(7s), 1481 - 1487. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/10803