Implementation of FPGA based Architecture to Detect and Remove Clutter in Automotive Radar using Signal Processing Algorithm

  • Syed Ameer Abbas S, Meer Thahira K

Abstract

In automotive Radar, Signal processing poses a significant challenge because of its computation time and data storage requirements. FPGA is effectively adapted for implementation of signal processing algorithms in advanced radar system design. In the proposed work, the Signal generator simulates the real world inputs with clutter in analog domain and sent to 8-bit analog to digital converter (ADC) with a sampling rate of 10 kilo samples per second. The sampled frequencies were fed into different modules viz. Hamming window, FFT, Square law detector and CA-CFAR which are implemented in FPGA. Hamming window is applied to limit the frequency content and reduce the spectral leakage caused by ADC, then FFT is applied to time domain samples. Square law detection is used to eliminate the negative terms obtained from FFT. CA-CFAR module has been used to eliminate the clutter for radar target detection. The radar signal processing algorithm is synthesized by Verilog HDL and implemented in Virtex-5 FPGA to provide better resolution and estimation performance which enables automotive radar technology that can be made available to all the on-road vehicles  

Published
2020-04-20
How to Cite
Syed Ameer Abbas S, Meer Thahira K. (2020). Implementation of FPGA based Architecture to Detect and Remove Clutter in Automotive Radar using Signal Processing Algorithm. International Journal of Advanced Science and Technology, 29(7s), 1201 - 1211. Retrieved from https://sersc.org/journals/index.php/IJAST/article/view/10690