Analysis of Low Power and High Speed Exclusive-OR Gate through MCML Tri-State Buffer
A new technique to implement exclusive-OR (XOR) gate by using MOS current mode logic (MCML) low-power Tristate buffer concept. The design of the Proposed MCML XOR gate is carried out through analytical modeling of its static parameters and the performance is compared with the traditional CMOS XOR gate. The theoretical propositions are validated through using 45nm CMOS technology. This area simulates the exclusive-OR (XOR) gate design using MCML Tristate buffer and with the existing traditional exclusive-0R gate design in 45nm technology using cadence virtuoso tool. The circuit schematic designed and the circuits are simulated for functionality verification.