High Throughput and Mixed Radix N-Point Parallel Pipelined FFT VLSI Architectures for Advanced Wireless Communication

  • K Vijayakanthan, Hemachandran K, M Anand, M Janakirani


In this paper,high throughput mixed radix N-Point (N = 128, 256, 512, 1024, 2048)parallelpipelined Variable Length Fast Fourier Transform (FFT) Very Large Scale Integration (VLSI) architectures for Long Term Evolution (LTE)-Multiple-Input-Multiple-Output (MIMO) applications. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA Deviceto analyze the performance metrics. The proposed FFT architectures have been designed and implemented to deliver throughput of 550Mega-Samples-Per-Second (MSPS) at a sampling rate of 550 MHz clock frequency. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme DSP/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed pipelined FFT 2048-point architecturesexhibit very low latencyof 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. The designed FFTprocessorprovides the very high throughput rate in order to meet the LTE specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better Power Delay Productwith extra hardware as trade-off.